1. Field of the Invention
This invention relates to a simplified method of manufacturing a bipolar transistor.
2. Description of the Prior Art
In order to obtain an integrated circuit capable of high speed operations, it is necessary to reduce the size of the bipolar transistor therein. However, the method of achieving the desired size reduction must result in a product having a degree of realiability.
The photolithography process of manufacturing is generally employed, at present, and its accuracy is on the order of 1.mu..
In the photolithograph process, the IC's are manufactured by the so-called planar method. This manufacturing method comprises a series of manufacturing process steps such as isolation diffusion, collector contact diffusion and resistor diffusion, etc. This series of process steps requires highly accurate mutual positional relationships between the diffusion areas.
Generally, a composed mask method is used in manufacturing high density IC's, in order to meet the above positional requirements. In the composed mask method, the same mask (called the composed mask) provides the pattern for forming the abovementioned isolation diffusion window, collector contact window, base diffusion window and resistance diffusion window. The windows are simultaneously provided at one time on a specific insulation film, for example, on the silicon nitride which covers the semiconductor substrate surface. In other words, this composed mask method utilizes a self-aligning principle. The idea of the composed mask method is also applicable for providing each electrode of the emitter, base, collector and resistor, and is also applicable to the manufacture of high density IC's. The composed mask method is explained in detail in the following description and is very important with respect to the present invention.
To illustrate the prior art method of constructing IC's, reference is made to FIGS. 1-4.
FIG. 1 shows a partial cross-section of a P- type substrate 10, upon which process steps have been performed, up to and including the step of base diffusion by the composed mask method. Namely, after performing an impurity diffusion step forming the buried N+ layer 11 on the P- type silicon substrate 10, the epitaxial N type layer 12 is grown thereon. A thin oxide film 13 covers the layer 12. A silicon nitride film 14 is coated on the thin oxide film 13 by chemical vapor deposition process and a silicon dioxide film 15 is subsequently coated thereon. A photo resist is coated on the surface of film 15, exposed and developed by using above-mentioned composed mask. The film 15, in areas which are to be subject to isolation diffusion, collector contact diffusion, base diffusion and resistor diffusion, is selectively removed by hydrofluoric etching.
The substrate 10 is then dipped into boiling phosphoric acid wherein the film 15 is used as a mask and only the exposed silicon nitride film 14 is etched. Thus, an isolation diffusion window 16, a collector contact diffusion window 17 and a base diffusion window 18 are formed in the silicon nitride film 14.
The oxide film 13, in the window 16, is then removed by a conventional photolithography method and a P+ type impurity is diffused through window 16 into the epitaxial layer 12 to form the isolation region 19.
The oxide film 13, in the window 17, is separately removed by a second photolithography method, and an N+ type impurity is diffused into the epitaxial layer 12 through window 17 to thereby form an N+ collector contact region 20.
Finally, the oxide film 13, in the window 18, is removed and P type impurity is diffused into the epitaxial layer through this window, thus forming the P base region 21.
By previously forming the windows 16, 17 and 18 in the nitride film 14, the positional relation between them is inevitably limited. Therefore, it is unnecessary to obtain positional alignment as each window is sequentially formed, since the window which is the same as that provided on the nitride film 14 corresponds to the window formed in the film 13, and, by this reason, alignment is simplified.
The idea of the composed mask mentioned above can also be applied to the formation of each electrode. As shown in FIGS. 2 and 3, chemical vapor deposition is applied to the surface and thereby a second layer of silicon nitride 22 and a second layer of silicon dioxide 23 are formed. Then, an emitter diffusion window 24, a base electrode window 25 and a collector contact window 26 are formed in the second silicon nitride 22 by using a composed mask different from that employed in conjunction with the FIG. 1 description. The oxide film 13 again present in exposed windows 24 and 26 is removed by the photolithography method and a poly-crystalline silicon layer 27 is coated over the entire surface, as is shown in FIG. 3. A phosphosilicate glass layer 28 is coated thereover. The phosphorous, in the layer 28, is diffused into the epitaxial layer 12 by passing through the silicon layer 27 at the windows 24 and 26 to thereby form an N+ emitter region 29 and an N+ collector contact region 30.
After the emitter diffusion, surface layer 28 is entirely removed. Then, the silicon layer 27 and oxide film 13, in the base electrode window 25, are also removed by the photolithography method.
In FIG. 4, an aluminum layer 31 is shown which was coated on the entire surface and then selectively removed to form an electrode wiring pattern after sintering. Thus, an emitter electrode 32, a base electrode 33 and a collector electrode 34 are formed.
The bipolar transistor, manufactured by the above-mentioned prior art manufacturing method illustrated in FIGS. 1-4, has a polysilicon layer 27 between the emitter electrode 32 and emitter region 29. Therefore, during sintering to obtain an ohmic contact between the emitter electrode 32 and the emitter region 29, the eutectic alloy of aluminum and silicon forming the electrode will not reach the PN junction between emitter and base. Thereby, a high speed and high density IC is manufactured with a very shallow emitter region.
However, in the course of executing the above-mentioned prior art manufacturing method, a basic defective feature has been found. When etching the oxide film 13, in the base electrode window, by using the nitride film 22 as the mask, the oxide film 13 tends to become over-etched in the area where the oxide film is relatively thin. Therefore, an overhang of the nitride film 22 is formed as shown in FIG. 4. An aluminum electrode subsequently provided at that etched portion, thereby may become open due to the nitride overhang. Such overhand is formed at the emitter electrode window 24 and the collector electrode window 26. However the polysilicon layer 27 covers the overhang due to the special method of chemical vapor deposition.
On the other hand, when providing an electrode window it is necessary to coat a silicon nitride film 22 and a silicon oxide film 23, which thereby makes the IC manufacturing process complex.